Conventionally, a semiconductor memory apparatus has been known that includes a first decoder to select a word line depending on an address signal, a second decoder to select a pair of bit lines depending on the address signal, a precharge circuit to precharge the pair of bit lines, and an equalizer circuit to equalize the pair of bit lines.
This semiconductor memory apparatus includes an address change detection circuit to detect a change of the address signal decoded by the first decoder, and a precharge control circuit and an equalizer control circuit that make the precharge circuit and the equalizer circuit operate, respectively, when the address change detection circuit detects an address change (see, for example, Patent Document 1).